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1 publication order number : lv8112vb/d www.onsemi.com ? semiconductor component s industries, llc, 2014 november 2014 - rev. 1 ordering information see detailed ordering and shipping info rmation on page 15 of this data sheet. lv8112vb overview the lv8112vb is a 3-phase brushless motor driver for polygon mirror motor driving of lbp. a circuit needed to drive of polygon mirror motor can be composed of a single-chip. also, the output transistor is made dmos by using bidc process, and by adopting the synchronous rectification method, the lower power consumption (heat generation) is achieved. feature ? 3-phase bipolar drive ? direct pwm drive + sy nchronous rectification ? i o max1 = 2.5a ? i o max2 = 3.0a (t ? 0.1ms) ? output current control circuit ? pll speed control circuit ? phase lock detection output (with mask function) ? current limiter, constraint protection, thermal shutdown, under-voltage protection circuit ? circuit to switch slowing down method while stopped (free run or short-circuit brake) ? constraint protection detection signal switching circuit (fg or ld) ? forward / reverse switching circuit ? compatible with hall fg ? hall bias pin (bias current cut in a stopped state) ? 5v regulator output ? sdcc function (speed detection current control) typical applications ? laser beam printer (lbp) ? plain paper copier (ppc) ? multi function printer (mfp) bi-cmos lsi 3-phase brushless motor driver for polygon mirror motor ssop44k(275mil) exposed pad
lv8112vb www.onsemi.com 2 specifications absolute maximum ratings at ta = 25 ? c parameter symbol conditions ratings unit supply voltage v cc max v cc pin 37 v vg max vg pin 42 v output current i o max1 *1 2.5 a i o max2 t ? 0.1ms *1 3.0 a allowable power dissipation pd max mounted on a specified board *2 1.7 w operation temperature topr -25 to +80 ? c storage temperature tstg -55 to +150 ? c junction temperature tj max 150 ? c *1. tj max = 150 ? c must not be exceeded. *2. specified board: 114.3mm 76.1mm 1.6mm, glass epoxy board. caution 1) absolute maximum ratings represent the va lue which cannot be exceeded for any length of time. caution 2) even when the device is used within the range of abso lute maximum ratings, as a result of continuous usage under hig h temperature, high current, high voltage, or drastic temperature change, the reliability of the ic may be degraded. please contact us for the further detai ls. recommended operating conditions at ta = 25 ? c parameter symbol conditions ratings unit supply voltage range v cc 10 to 35 v 5v constant voltage output current i reg 0 to -30 ma ld pin applied voltage v ld 0 to 5.5 v ld pin output current i ld 0 to 15 ma fg pin applied voltage v fg 0 to 5.5 v fg pin output current i fg 0 to 15 ma hb pin output current i hb 0 to -30 ma electrical characteristics at ta ? 25 ? c, v cc = 24v parameter symbol conditions ratings unit min typ max current drain i cc 1 5.5 6.5 ma i cc 2 in a stop state 1.0 1.5 ma 5v constant voltage output output voltage vreg 4.65 5.0 5.35 v line regulation ? vreg1 v cc = 10 to 35v 20 100 mv load regulation ? vreg2 i o = -5 to -20ma 25 60 mv temperature coefficient ? vreg3 design target value * 0 mv/ ? c output block output on resistance r on i o = 1a , sum of the lower and upper side outputs 1.5 1.9 ? output leakage current i o leak design target value * 10 ? a lower side diode forward voltage v d 1 i d = -1a 1.0 1.35 v upper side diode forward voltage v d 2 i d = 1a 1.0 1.35 v charge pump output (vg pin) output voltage vg out v cc +4.9 v cp1 pin output on resistance (high level) v oh (cp1) i cp1 = -2ma, design target value * 500 700 ? output on resistance (low level) v ol (cp1) i cp1 = 2ma 300 400 ? * design target value, do not measurement. continued on next page. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lv8112vb www.onsemi.com 3 continued from preceding page. parameter symbol conditions ratings unit min typ max hall amplifier block input bias current i hb (ha) -2 -0.5 ? a common mode input voltage range v icm 0.5 vreg-2.0 v hall input sensitivity 80 mvp-p hysteresis ? v in (ha) 15 24 42 mv input voltage l ? h v slh 12 mv input voltage h ? l v shl -12 mv hall bias (hb pin) p-channel output output voltage on resistance v ol (hb) i hb = -20ma 20 30 ? output leakage current i l (hb) v o = 0v 10 ? a fg amplifier schmitt block (in1) input amplifier gain g fg design target value * 5 times input hysteresis (h ? l) v shl (fgs) input referred, design target value * 0 mv input hysteresis (l ? h) v slh (fgs) input referred, design target value * 10 mv hysteresis v fgl input referred, design target value * 10 mv fgfil pin high level output voltage v oh (fgfil) 2.7 3.0 3.3 v low level output voltage v ol (fgfil) 0.75 0.85 0.95 v external capacitor charge current i chg 1 v chg 1 = 1.5v -5 -4 -3 ? a external capacitor discharge current i chg 2 v chg 2 = 1.5v 3 4 5 ? a amplitude v(fgfil) 1.95 2.15 2.35 vp-p fg output output on resistance v ol (fg) i fg = 7ma 20 30 ? output leakage current i l (fg) v o = 5.5v 10 ? a pwm oscillator high level output voltage v oh (pwm) 2.95 3.2 3.45 v low level output voltage v ol (pwm) 1.3 1.5 1.7 v external capacitor charge current i chg (pwm) v pwm = 2v -90 -70 -50 ? a oscillation frequency f(pwm) c = 150pf 180 225 270 khz amplitude v(pwm) 1.5 1.7 1.9 vp-p recommended operation frequency range f opr 15 300 khz csd oscillation circuit high level output voltage v oh (csd) 2.7 3.0 3.3 v low level output voltage v ol (csd) 0.8 1.0 1.2 v amplitude v(csd) 1.75 2.0 2.25 vp-p external capacitor charge current i chg 1(csd) v chg 1 = 2.0v -14 -10 -6 ? a external capacitor discharge current i chg 2(csd) v chg 2 = 2.0v 8 11 14 ? a oscillation frequency f(csd) c = 0.068 ? f, design target value * 30 40 50 hz phase comparing output output on resistance (high level) v pdh i oh = -100 ? a 500 700 ? output on resistance (low level) v pdl i ol = 100 ? a 500 700 ? phase lock detection output output on resistance v ol (ld) i ld = 10ma 20 30 ? output leakage current i l (ld) v o = 5.5v 10 ? a error amplifier block input offset voltage v io (er) design target value * -10 +10 mv input bias current i b (er) -1 +1 ? a high level output voltage v oh (er) i ei = -100 ? a ei+0.7 ei+0.85 ei+1.0 v low level output voltage v ol (er) i ei = 100 ? a ei-1.75 ei-1.6 ei-1.45 v dc bias level v b (er) -5% vreg/2 5% v * design target value, do not measurement. continued on next page.
lv8112vb www.onsemi.com 4 continued from preceding page. parameter symbol conditions ratings unit min typ max current control circuit drive gain gdf while phase locked 0.5 0.55 0.6 times current limiter circuit (pins rf and rfs) limiter voltage v rf 0.465 0.515 0.565 v under-voltage protection operation voltage vsd 8.3 8.7 9.1 v hysteresis ? vsd 0.2 0.35 0.5 v cld circuit external capacitor charge current i cld v cld = 0v -4.5 -3.0 -1.5 ? a operation voltage v h (cld) 3.25 3.5 3.75 v thermal shutdown operation thermal shutdown operation temperature tsd design target value (junction temperature) 150 175 ? c hysteresis ? tsd design target value (junction temperature) 30 ? c clk pin external input frequency f i (clk) 0.1 10 khz high level input voltage v ih (clk) 2.0 vreg v low level input voltage v il (clk) 0 1.0 v input open voltage v io (clk) vreg-0.5 vreg v hysteresis v is (clk) 0.2 0.3 0.4 v high level input current i ih (clk) v clk = vreg -10 0 +10 ? a low level input current i il (clk) v clk = 0v -110 -85 -60 ? a csdsel pin high level input voltage v ih (csd) 2.0 vreg v low level input voltage v il (csd) 0 1.0 v input open voltage v io (csd) vreg-0.5 vreg v high level input current i ih (csd) v csdsel = vreg -10 0 +10 ? a low level input current i il (csd) v csdsel = 0v -110 -85 -60 ? a s/s pin high level input voltage v ih (ss) 2.0 vreg v low level input voltage v il (ss) 0 1.0 v input open voltage v io (ss) vreg-0.5 vreg v hysteresis v is (ss) 0.2 0.3 0.4 v high level input current i ih (ss) v s/s = vreg -10 0 +10 ? a low level input current i il (ss) v s/s =0v -110 -85 -60 ? a brsel pin high level input voltage v ih (brsel) 2.0 vreg v low level input voltage v il (brsel) 0 1.0 v input open voltage v io (brsel) vreg-0.5 vreg v high level input current i ih (brsel) v brsel = vreg -10 0 +10 ? a low level input current i il (brsel) v brsel = 0v -110 -85 -60 ? a f/r pin high level input voltage v ih (fr) 2.0 vreg v low level input voltage v il (fr) 0 1.0 v input open voltage v io (fr) vreg-0.5 vreg v high level input current i ih (fr) v f/r = vreg -10 0 +10 ? a low level input current i il (fr) v f/r = 0v -110 -85 -60 ? a * design target value, do not measurement. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lv8112vb www.onsemi.com 5 package dimensions unit : mm ssop44k (275mil) exposed pad case 940af issue a
lv8112vb www.onsemi.com 6 soldering footprint* *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. (unit: mm) 7.00 0.32 1.00 0.65 (4.7) (3.5) notes: 1. the measurements are for reference only, and unable to guarantee. 2. please take appropriate action to design the actual exposed die pad and fin portion. 3. after setting, verification on the product must be done. (although there are no recommended design for exposed die pad and fin portion metal mask and shape for through-hole pitch (pitch & via etc), checking the soldered joint condition and reliability verification of soldered joint will be needed. void gradient insufficient thickness of soldered joint or bond degradation could lead ic destruction because thermal conduction to substrate becomes poor.) xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. may or may not be present. xxxxxxxxxx ymddd
lv8112vb www.onsemi.com 7 -25 0 25 50 80 100 0 2.0 1.5 1.0 0.5 pd max -- ta 1.7 0.95 ambient temperature, ta -- c allowable power dissipation, pd max -- w 75 pin assignment 44 43 42 41 40 39 38 37 29 30 31 32 33 34 35 36 23 24 25 26 27 28 1 clk 2 ld 3 s/s 4 vreg 5 brsel 6 csdsel 7 f/r 8 cld 16 15 14 13 12 11 10 9 22 21 20 19 18 17 csd fg pwm fc fgfil ph pd ei eo toc gnd hb cp2 cp1 vg v cc 1 v cc 2 rfs rf out1 out2 out3 gnd2 sub in3 ? in3 + in2 ? in2 + in1 ? in1 + lv8111v top view lv8112vb
lv8112vb www.onsemi.com 8 block diagram and application circuit example csdsel csd osc brsel s/s f/r count logic ld ld mask clk pll fg filter hall hys amp hb curr lim control circuit logic pwm osc comp cont amp peak hold vreg lvsd driver charge pump vreg pd ei eo toc fc ph vreg v cc 1 v cc 2 vg cp1 cp2 v cc out1 out2 out3 gnd2 sub gnd rf rfs hb in1 + in2 + in3 + in1 ? in2 ? in3 ? fgfil fg clk cld ld f/r s/s brsel csd csdsel pwm ld output clk input fg output tsd
lv8112vb www.onsemi.com 9 pin function pin no. pin name function equivalent circuit 1 clk clock input pin (10khz maximum) 1 5k 10k 55k vreg 2 ld phase lock detection output pin. goes on during pll-phase lock. open drain output. 2 vreg 3 s/s start/stop input pin. start with low-level input. stop with high-level input or open input 3 5k 10k 55k vreg 4 vreg 5v regulator output pin. (the control circuit power supply) connect a capacitor between this pin and gnd for stabilization. 4 v cc 50 5 brsel brake selection pin. by low-level, short-circuit braking when the s/s pin is in a stopped state. (brake for the inspection process) 5 5k 55k vreg 6 csdsel motor constraint protection detection signal selection pin. select fg with low, and ld with high or in an open state. 6 5k 55k vreg continued on next page.
lv8112vb www.onsemi.com 10 continued from preceding page. pin no. pin name function equivalent circuit 7 f/r forward / reverse selection pin. 7 5k 55k vreg 8 cld phase lock signal mask time setting pin. connect a capacitor between this pin and gnd. when it is not necessary to mask, this pin must be left open. 8 500 vreg 2k 9 csd pin for both the constraint protection circuit operation time setting and the initial reset pulse setting. connect a capacitor between this pin and gnd. if the motor constraint protection circuit is not used, a capacitor and a resistor must be connected in parallel between the csd pin and gnd. 9 500 vreg 10 fg fg schmitt output pin. open drain output. 10 vreg 12 pwm pin to set the oscillation frequency of pwm. connect a capacitor between this pin and gnd. 12 vreg 200 2k 14 fc frequency characte ristics correction pin of the current control circuit. connect a capacitor between this pin and gnd. 14 vreg 500 110k continued on next page.
lv8112vb www.onsemi.com 11 continued from preceding page. pin no. pin name function equivalent circuit 15 fgfil fg filter pin. when the noise of the fg signal is a problem, connect a capacitor between this pin and gnd. 15 vreg 16 ph pin to stabilize the rf waveform. connect a capacitor between this pin and gnd. 16 vreg 500 10k 17 pd phase comparison output pin. the phase error is output by using the duty changes of the pulse. 17 vreg 500 18 ei error amplifier input pin. 18 vreg 500 19 eo error amplifier output pin. vreg 100k 19 20 toc torque command voltage input pin. normally, this pin must be connected with the eo pin. on-duty of upper-side output tr increases when the toc voltage decreases. 20 vreg 21 gnd ground pin of the control circuit block. continued on next page.
lv8112vb www.onsemi.com 12 continued from preceding page. pin no. pin name function equivalent circuit 22 hb hall element bias current pin. goes on when the s/s pin is in a start state. goes off when the s/s pin is in a stopped state. 22 vreg 23 24 25 26 27 28 in1 + in1 ?? in2 + in2 ?? in3 + in3 ? hall amplifier input pin. a high-level state of logic is recognized when in + > in ? . reverse case is a low-level state. the input amplitude of 100mvp-p or more (differential) is desirable in the hall inputs. when the noise of the hall signal is a problem, connect the capacitors between in + and in ? . 25 vreg 500 500 26 24 28 27 23 29 sub frame ground pin. connect this pin with the gnd2 pin. 30 gnd2 ground pin of the output circuit block. 32 34 36 out3 out2 out1 output pin. as for pwm, a duty control is executed on the upper side fet. 38 rf source pin of output mosfet (lower). connect low resister (rf) between this pin and gnd. 39 rfs output current detection pin. connect this pin to the rf pin. 39 5k vreg 40 v cc 2 power supply pin for output. connect a capacitor between this pin and gnd for stabilization. 41 v cc 1 power supply pin for control. 42 vg charge pump output pin (power supply for the upper side fet gate). connect a capacitor between this pin and v cc . 43 44 cp1 cp2 pin to connect a capacitor for charge pump. connect a capacitor between cp1 and cp2. 32 v cc 34 36 38 v cc 44 500 42 43 100
lv8112vb www.onsemi.com 13 3-phase logic truth table (in = ?h? indicates the state where in in + > in ? ) f/r = h f/r = l output in1 in2 in3 in1 in2 in3 out1 out2 out3 h l h l h l l h m h l l l h h l m h h h l l l h m l h l h l h l h h l m l h h h l l h m l l l h h h l m h l s/s pin brsel pin input state mode input state while stopped high or open stop high or open free run low start low short-circuit brake csdsel pin selection of sdcc function input state mode input state mode high or open ld standard f/r = high or open function on low fg standard f/r = low function off lv8112vb description 1. speed control circuit this ic can realize a high efficien cy, low-jitter, a stable rotation by adopting the pll speed control method. this pll circuit compares the phase difference of the edge between the clk signal and the fg signal and controls by using the output of error. the fg servo frequency under control becomes congruent with the clk frequency. f fg (servo) = f clk 2. output drive circuit this ic adopts the direct pwm drive method to reduce power loss in the output. the driving force of the motor is adjusted by changing the on-duty of the output transistor. the pwm switching of the output is performed by the upper-side output transistor. also, this ic has a parasitic diode of the output dmos as a regeneration route when the pwm switching is off. but, this ic is cut down the fever than the diode re generation by performing synchronous rectification. 3. current limiter circuit this ic limits the (peak) current at the value i = v rf / rf (v rf = 0.515v (typical), rf : current detection resister). the current limitation operation consists of reducing the pwm output on duty to suppress the current. to prevent malfunction of the current limitation operation when the reverse recovery current of diode is detected, the operation has a delay (approximately 300ns). since the current change at the motor start-up is fast when the motor coil is lower resistance or smaller inductan ce, the current more than the setting value may flow during this delay time. in this case, it is necessary to set the limiter value considering the current that increased by the delay. 4. power saving circuit this ic becomes the power saving state of decreasing the cons umption current in the stop stat e. the bias current of the majority circuits is cut in the power saving state. also, 5v regulator output is output in the power saving state. 5. reference clock note that externally-applied clock signal has no noise of chattering. the input circuit has a hysteresis. but, if noise is a problem, that noise must be excluded by inserting capacitor. when the ic is switched to the start state if the reference cloc k is no input, the drive is turned off after a few rotations if the motor constraint protection circuit is used. (clock disconnection protection)
lv8112vb www.onsemi.com 14 6. pwm frequency the pwm frequency is determined by using a capacitor c (f) connected to the pwm pin. f pwm ? 1 / (29500 ? c ) ? 150pf or more f pwm ? 1 / (32000 ? c ) ? 100pf or more, less than 150pf the frequency is oscillated at about 225khz when a capacitor of 150pf is connected. the gnd of a capacitor must be placed as close to the cont rol block gnd (gnd pin) of the ic as possible to reduce influence of the output. 7. hall effect sensor input signals the signal input of the amplitude of hysteresis of 42mv max or more is required in the hall effect sensor inputs. also, an input amplitude of over 100mvp-p is desirable in the hall effect sensor inputs in view of influence of noise. if the output waveform (when the phase changes ) is distorted by noise, that noise must be excluded by inputting capacitors across the inputs. 8. fg signal the hall signal of in1 is used as the fg signal in the ic . if noise is a problem, the no ise of the fg signal can be excluded by inserting a capacitor between the fgfil pin and gnd. but note that normal operation becomes impossible if the value of the capacitor is overlarge. also, note that the trouble of nois e occurs easily when the position of gnd of the capacitor is incorrect. 9. constraint protection circuit this ic has an on-chip constraint protection circuit to protect the ic and the motor in motor constraint mode. when the csdsel pin is set to the high level or open input, if the ld output remains high (unlocked statement) for a fixed period in the start state, this circuit operates. in the low level setting case, if the fg signal is not switched for a fixed period in the start state, this circuit operates. also, the upp er-side output transistor is turned off while the constraint protection circuit is operating. this time is set by the capacitance of the capacitor connected to the csd pin. the set time (in seconds) is 102 ? c ( ? f) when a capacitor of 0.068 ? f is connected, the protection tim e becomes about 7.0 seconds. the set time must be set well in advanc e for the motor start-up tim e. when the motor is d ecelerated by switching the clock frequency, this protection circuit is not operated. to re lease the constraint protection state, put the s/s pin into the start again after the stop state, or tu rn on the power supply again after the tu rn off state. the cs d pin has a function as the power-on reset pin also. if the csd pin is connected to gnd, the logic circuit goes to the reset state and the speed cannot be controlled. therefore, if the constraint protection circuit is not used, a resistor of about 220k ? and a capacitor of about 4700pf must be connected in parallel between the csd pin and gnd. 10. phase lock signal (1) phase lock range this ic has no the speed system counter. the speed error range in the phase lock state is indeterminable only by the characteristics of the ic. ( because the accelerations of the change in fg frequency influences.) when it is necessary to specify for the speed error as a motor, the value obtained while the motor is actually operating must be measured. since the speed error is likely to occur when th e acceleration of fg is la rger, the speed error will be the largest when the ic goes into the lock state at mo tor start-up, or the unlock state by switching the clock. (2) phase lock signal mask function this function can mask the short lock signal that occurred by the hunting when it goes into the lock state. therefore, the ic will be able to output the stable lock signal. but the mask time causes the delay of the lock signal output. the mask time is set by the capaci tance of the capacitor connected between the cld pin and gnd. the mask time (seconds) is 1.8 ? c ( ? f) when a 0.1 ? f capacitor is connected, the ma sk time becomes about 180ms. set the enough mask time if it must be masked completely. when there is no need for masking, the cld pin must be left open.
lv8112vb www.onsemi.com 15 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc pro ducts are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that sci llc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner. 11. power supply stabilization since this ic adopts the method of the switching drive for the application that flows la rge output current, the power supply line is relatively fluctuated. therefore, the sufficie nt capacitors to stabilize the power supply voltage must be connected between the v cc pin and gnd as close to the pin as possible. the ground-side of the capacitors must be connected to the gnd2 pin that is gnd of the output circuit block. if it is impossible to connect a capacitor (electrolytic capacitor) near the pin, the ceramic capacitor of about 0.1 ? f must be connected as close to the pin as possible. since the power supply line is more fluc tuated when the diodes are inserted in the power supply line to prevent ic destruction due to the reverse connection of th e power supply, choose even larger capacitors. 12. vreg stabilization to stabilize the vreg voltage that is the power supply of the control circuit, connect a capacitor of 0.1 ? f or more. the ground-side of the capacitor must be connected as close to the control block gnd (gnd pin) of the ic as possible. 13. error amplifier external components of the error amplifier block must be placed as close to the ic as possi ble to reduce influence of noise. also, these components must be placed as far as possible from the motor. 14. metal of ic?s backside the heat radiation can be efficiently diffused by soldering the metal of ic?s backside to the printed circuit board. 15. sdcc (speed detection current control) the sdcc function controls the current limiter value by sensing the motor speed. when the rotation speed exceeds 95% of the target speed, this function decreases the cu rrent limiter value to 87.5% and reduces the acceleration of the motor. therefore, it stabilizes the phase lock pull-in and im proves the variance of the motor start-up time. the sdcc function b ecomes as follows: f/r = high or open function on f/r = low function off note: if the rotation direction of the motor does not match the selected state of sdcc, it is necessary to adapt by reversing the polarity terminal of the hall bias. ordering information device package shipping (qty / packing) LV8112VB-AH ssop44k (275mil) ep (pb-free / halogen free) 2000 / tape & reel

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